Rupert Swarbrick

Bool parameters which default to enabled can't be disabled

4

If a core file specifies a boolean parameter like this (taken from Ibex): ``` RV32M: datatype: bool paramtype: vlogparam default: true description: Enable the M ISA extension (hardware multiply/divide) ```...

Add new warning on unused waivers

14

When you're implementing something in stages, it's quite common to have signals tied off that you'll connect to in future. Verilator (and other tools) support magic signals starting with `unused`,...

UNOPTFLAT lint warning (for tree arbiter)

3

If you download the attached `prim_arbiter_tree.sv` and run Verilator lint on it, you see the following warnings: ``` > verilator --lint-only -Wno-ALWCOMBORDER tst/prim_arbiter_tree.sv %Warning-UNOPTFLAT: tst/prim_arbiter_tree.sv:45:39: Signal unoptimizable: Feedback to clock...

[icache,dv] Minor tidyups after dropping PMP interface

5

Tom's RTL changes at https://github.com/lowRISC/ibex/pull/1474 simplify things dramatically on the DV side, which is nice. I made some suggested simplifications on that PR and there are probably further simplifications possible....

Rip out all the non-cosim stuff from dv/uvm/core-ibex scripts

4

Depends on #1565 but, once we've got working "cosim tooling", we should get rid of the old way of doing things. This doesn't include the work to rip out the...

riscv_csr_test fails because we don't model MCAUSE properly

3

*Copying from https://github.com/lowRISC/ibex/issues/1658#issuecomment-1129412757 (a silly place for me to have put this text in the first place)* Running the `riscv_csr_test` with ``` make -j4 ITERATIONS=1 SEED=1 TEST=riscv_csr_test VERBOSE=1 SIMULATOR=xlm WAVES=1...

Teach auto-generated interrupt handlers to clear interrupts again

2

It would be nice if we could customise our (new) sequences that drive interrupts to drop the interrupts again only when they were acknowledged. (Ibex has level-, rather than edge-triggered...

Migrate all remaining test sequences to use cosim

5

Figure out what needs to be done with e.g. the self-checking interrupt sequences now that we're using cosimulation. Do it! > estimate 32

Add support for passing fixed binaries to our uvm/core_ibex regression flow

3

> estimate 4

[ci] Let's try to integrate a Yosys synthesis flow into CI

4

The guys at Antmicro have been working on their Surelog+UHDM+Yosys flow and it seems that it can now build Ibex with vanilla Yosys plus their stuff as a plugin. It...