Rupert Swarbrick

I notice that the first PC that is reported is 0x00100000, but your code starts at `_start`, which has address `0x0010054`. And the reported instruction contents are `0x464c457f`, which don't...

I'd suggest taking a look at the simulation trace that's coming out. Notice that the cycle counter in the first column is now going up by 80 each line (instead...

This module got vendored in from OpenTitan (which has an entropy distribution network, which `prim_edn_req` connects to). But the end result is a little silly! I suspect the sensible fix...

This looks like a sensible change to me. (And the VCS support in that file was written by me, back in 2020!) Are you happy to open a PR with...

Hmm, that's odd. Could you generate a simple example firmware (a few lines of assembly!) that shows the problem and paste the code here? I'm also a bit confused because...

Ok, thanks for the response. I'm afraid that I still don't quite understand what's wrong with what you're seeing. Please could you follow up with an example of some firmware,...

Hi there! I'm not sure exactly what has gone wrong, but any failure must have happened just before the line that says ` make[1]: *** [out/metadata/tb.compile.stamp] Error 2`. (Note: the...

Well, the first failure happens when running VCS. See line 11, which ends with "Error 2". You're right that some things look a bit dubious below (maybe you're using an...

Thanks for the report. I've taken a look, and the `riscv_bitmanip_full_test` test requires a full bitmanip implementation. We don't have one with the OpenTitan configuration, which is what you've selected...

Ok, cool. I guess the remaining question is whether there's a "run everything I need" command that caused `riscv_bitmanip_full_test` to run with `IBEX_CONFIG=opentitan`. If so, there's some filtering we need...