Rupert Swarbrick

All sorted, thanks. Let's rebase onto the current head of master and I think we should be good to review and merge :-)

This is unchecked, but can't we simplify this a bit? I'm imagining something like ```systemverilog task progbuf_rw(int idx); uvm_reg_data_t data = $urandom; uvm_reg_data_t r_data; csr_wr(.ptr(jtag_dmi_ral.progbuf[i]), .value(data)); csr_rd(.ptr(tl_mem_ral.program_buffer[i]), .value(r_data)); `DV_CHECK_EQ(data, r_data)...

I agree that this you're correctly describing what the code currently does :-) But I'm trying to say that this is currently testing a reasonably trivial property ("writes to X...

Sorry for the slow reply. But I'm clearly missing something! Are you saying that it's impossible to do a CSR read over the DMI interface? I don't *think* that's true....

I'm so sorry: I wrote something rather silly yesterday. You were pointing out that the TL CSR interface here is read-only, so it only makes sense to send data in...

I'm convinced! About the coverage report, I believe that verification of `rv_plic` is FPV-based (e.g. looking at `hw/ip_templates/rv_plic/doc/dv/README.md`). So I'm not sure we're going to have any way to make...

Hi @nbdd0121! Is this still something that we should be doing? It looks sensible to me: maybe it's worth rebasing?

Thanks for addressing the nitty comments from me. I'll leave it for someone who knows more about USB (@alees24 ?) to look through the logic properly.

Hi there! The only CI check that is failing is a (rather flaky) FPGA test which will not be affected by this change. So nothing to worry about there :-)...

Hi @MubashirSaleem775, Yes, I think we're planning to look at this in the coming week. It's a bit concerning that we're still writing new vseqs when some tests fail. At...