Rupert Swarbrick

I just checked, and the `--verilog-data-width` option got added to binutils in version 2.33 (back in 2019). (Thanks for the heads-up! It's cool!) I'm reasonably sure that this is ancient...

@hcallahan-lowrisc: Would you mind taking a look at this? It looks like something (`rtl_log`?) is not getting substituted properly in riscvdv_interface.py and I think you're the person who wrote most...

I suppose that a way to preserve compatibility would be an optional two-stage branch process. So you'd add something like a new `beq_hardened` which would decode as an illegal instruction...

Hi there! Sorry for the slow response. I'm a bit confused because I don't see these errors when I build locally. When I start with a clean repository, I see...

Ahh! Sorry for the stupidity: I had misread the version number in your original report. The error about `decoded_str` is a bit weird. As far as I can tell, Verilator...

Hi there, and thanks for the message. Could you give us a little more information about how to reproduce this? Maybe a seed for the test? I just ran `make...

Hi there, I'm sorry, but I can't actually find that SHA in either Ibex or our spike clone (riscv-isa-sim). Please could you reply with a description of what exactly you...

Hmm, this is odd. It *might* be that the problem is only shown by VCS (we mostly use Xcelium for our testing). This is a bit silly, but could you...

Ah, well the missing macro is also caused by an ordering problem. I think VCS is internally concatenating files in a different order from what Xcelium happens to choose. That...

Hi there! It turns out that I also spent some time last week getting stuff working with VCS. I *think* that PR #2037 should get everything working for you again....