riscv-perf-model
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
The implementation is based on the previous work by Vineeth. However I made change to use a single pipeline and reduce the number of events generated inside the Dache. I...
We are going to make changes to our fork of dromajo. I went to the Olympia read me on traces, to verify that a specific SHA for olympia/dromajo clone/build is...
Recording the requests for enhancements to FSL that came up during the review: From Arup: _Is there a way to fuse one or more classes of instruction with other instructions?...
PR Goals: Implement basic vector support for VALU operations, UOp generation for LMUL > 1, and vset support. The goal in this stage to design all necessary components to support...
So, the existing implementation is functionally correct and operates as follows: All SYS instructions bypass the execution step and proceed directly to the ROB. When the instruction is retired, the...
I'm trying to compile with CMAKE_BUILD_TYPE=Profile but I'm getting the following error: ``` /home/dan/anaconda3/envs/sparta/bin/../lib/gcc/x86_64-conda-linux-gnu/12.3.0/../../../../x86_64-conda-linux-gnu/bin/ld: /home/dan/anaconda3/envs/sparta/bin/../x86_64-conda-linux-gnu/sysroot/usr/lib/../lib/gcrt1.o: relocation R_X86_64_32S against symbol `__libc_csu_fini' can not be used when making a PIE object; recompile...
Adding an L1 Instruction Cache for fetch as noted in #143 - Updated fetch unit so that it requests a block of instructions per cycle from the instruction cache. The...
#### Limitations of the Current Cache model: - It cannot handle multiple misses. It is a blocking cache. #### Improvements to be made: - Design a non-blocking cache (Modelled similar...
I have been reviewing the STF trace generation support in Dromajo and have some recommendations to improve the implementation. * Add register read and write records * Add memory read...
As the branch prediction API is coming to a close, I'd like to propose adding a decoupled frontend with an L1 instruction cache. I did cover some of this with...
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model