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Published 20 hours ago • verified publisher icon riscv-software-src

Add L1 Instruction Cache

Open danbone opened this issue 1 year ago • 3 comments

Adding an L1 Instruction Cache for fetch as noted in #143

  • Updated fetch unit so that it requests a block of instructions per cycle from the instruction cache. The block is formed based on the instruction's program counters.
  • Tidied up some coding style within the L2Cache/MSS.
  • Added tests for new instruction cache unit.
  • Changed MSS credit interfaces to be more like those used within the core.

danbone avatar Feb 08 '24 13:02 danbone

I haven't managed to make much progress this week, rather than leave the PR to rot. I think I'd merge this and update #143 with the enhancements I'd hope to do, and open a new PR. Probably makes code review easier anyways.

danbone avatar Feb 16 '24 12:02 danbone

@danbone are you planning to add a documentation describing uarch of the modeled L1 Icache and changes to the fetch unit as a part of this PR?

arupc-qcom avatar Mar 04 '24 01:03 arupc-qcom

What is the status of this PR? I see it now has conflicts, if those were fixed is this ready to go?

I have a need in BPU evals.

jeffnye-gh avatar Aug 30 '24 18:08 jeffnye-gh