riscv-perf-model
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enhancements to Fusion/Fracture Specification Language (FSL)
Recording the requests for enhancements to FSL that came up during the review:
From Arup: Is there a way to fuse one or more classes of instruction with other instructions? For example, is there a way to define a logical immediate class of instructions for andi, ori, xori and define a sequence in terms of that class, instead of individual instructions?
- Add support in the syntax/parser for composition in expressing sequences. Add syntax for expressing the composition and for combining them from other sequences. Add the syntax description, add support in the parser and back end.
From Arup: If we do not anticipate having more than one sequence, constraint and conversion clause per transform, wondering if we need to specify the arguments iop1, seq1, cons1 in the agument lists for every transform. Instead, is it okay to make them implicit?
- Relax the requirement for argument lists in clauses in transforms using the encapsulated style. Change the syntax description, show examples, support in the parser and backend
Here is what I propose to address #1 instruction 'classes' or composition, and #2 reduction in some boiler plate, argument lists etc.
// ----------------------------------------------------------------
// Using the sequence composition syntax
// ----------------------------------------------------------------
prolog plg
{
isa rv64gc
uarch oly
ioput iop
}
transform composition
{
prolog plg //new: prolog can be external and shared
gpr g1..9 //new: variable naming expansion syntax
//new: setof is a collection type
//new: hasAttr will scan the contents of the isa specification named rv64gc
//for objects with the rtype and logical attributes, 'rtype' and 'logical'
//must be known to the isa object.
setof r_bools = plg.rv64gc.hasAttr(rtype).hasAttr(logical)
//Specifying the operands, and therefore their types, is necessary for the implicit
//constraints of a sequence. e.g. if there is an immediate in one of the operand
//positions this sequence will not be matched.
sequence comp_seq_a {
r_bools g1, g2, g3
r_bools g4, g5, g6
r_bools g7, g8, g9
}
//Compare the write/read ports required by the sequence with
//the limits of the microarchitecture 'oly'
constraints {
comp_seq_a.writePorts() <= plg.oly.writePorts()
comp_seq_a.readPorts() <= plg.oly.readPorts()
}
//new: fsl is the standard library equivalent
//morph() combines the sequence as specified by the
//user defined function object registered with the Fusion API
//by default this just calls the mavis equivalent
conversion {
//declare an instruction object, initialize using the fsl.morph()
//operation performed on the sequence
instr i_comp(fsl.morph(comp_seq_a))
//by default the mnemonic is the same as the instr object name.
//this can be overridden
i_comp.mnemonic("r_bool")
//this is using the replace idiom, the sequence objects in .input
//are removed and replaced with the instruction created by morphing.
plg.iop.input.replace(comp_seq_a,i_comp)
}
EDIT: corrected a set of typo's related to the sequence name, all references to the sequence name now correctly reference comp_seq_a, it was _b in some places.
Closing this. See the FSL submodule documentation.