riscv-perf-model
riscv-perf-model copied to clipboard
Non blocking cache implementation
The implementation is based on the previous work by Vineeth. However I made change to use a single pipeline and reduce the number of events generated inside the Dache. I has also removed the col-easing of the mshr requests (based on the block address) instead each request generates an mshr and the same instruction is then sent to next cache for lookup in case of a miss.
Micro architecture details https://docs.google.com/document/d/1HLlCkfZUtt6BafgVypS5pwS90zo4XOrGFOR1KIzYHLw/edit?usp=sharing