riscv-perf-model
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riscv-software-src
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Getting this error on M1 Macbook Air running OSX Ventura 13.3.1 when trying to build via [conda](https://github.com/riscv-software-src/riscv-perf-model/tree/master/conda). I was able to still run Olympia by skipping this step and just...
For STF reading (and possibly JSON), when the core is flushed, Fetch needs to refetch instructions from the flushed point. Currently it just flushes and keeps going.
I have been trying to run argos.py as given in the [tutorial](https://github.com/riscv-software-src/riscv-perf-model/wiki/Tutorial): `python $MAP_BASE/helios/pipeViewer/pipe_view/argos.py -d small_core_pipeout -l ../layouts/small_core.alf`. However, running this command gives me the following errors: `/usr/local/lib/libsimdb.so: undefined symbol:...
build fix for aaron's issue [#189 ](https://github.com/riscv-software-src/riscv-perf-model/issues/189) I have added checks to CMakeLists for Flex 2.6.4 and Bison 3.8.2. This is a likely cause but I can not duplicate the...
- Introduced support for multiple load/store pipelines by using vectors for queues, pipelines, and ready queues. Each pipeline can be managed independently. - Added mutexes (`cache_mutex_` and `tlb_mutex_`) to manage...
We propose a project to explore/compare the performance characteristics when instruction operations are fused in the machine alone and when the machine is assisted by a fusion aware compiler. The...
Missing `#include ` at [DecoderTypes](https://github.com/sparcians/mavis/blob/055b22aedf891ab2e41b2e3ca0164e85d4f20484/mavis/DecoderTypes.h) Which is fixed in a recent commit
Running into this issue after merging in the most recent FSL changes into my local branch, trying to build Olympia to test VLSU changes but this is blocking my build...
PR Goal: Implement VLSU instruction support. Current implementation uses the LSU design and adds vector iterations based on VLEN and data width of VLSU.
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model