riscv-perf-model
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
In the decode stage, we might find several pairs of uops that can be merged into one instruction to increase performance. Since this optimization is common in modern high-performance CPUs,...
Similar to requirements of a branch prediction API, add a prefetching API to Olympia and integrate or implement basic data/instruction prefetchers into the model. The effort would be: - [...
Add support for N load/store pipelines; this entails ensuring there are no collisions on the cache/mmu blocks between pipes (or add explicit support to allow that and assert when NOT...
The load/store unit in the RISC-V Performance Model is a simple, single, in-order, pipeline ([sparta::Pipeline](https://sparcians.github.io/map/classsparta_1_1Pipeline.html)) with a fixed number of stages: MMU Lookup, Cache lookup, and completion. To enhance this...
Can we modify Olympia such that it always outputs the git SHA used to build the simulator? This will be helpful for reproducibility.
Try out the steps to generate dhrystone stf trace following instructions from https://github.com/riscv-software-src/riscv-perf-model/blob/master/traces/README.md . This is the suggested order of operations: - replicate the current instructions in the README using...
Need a branch predictor to Fetch. Open to considerations on the type. Should be parameterized, but a common API would be beneficial to keep the model generic. Resolutions of the...
- Create a new sparta unit for L2Cache that received requests from IL1 and DL1 and sends requests out to BIU for the misses in L2Cache. - L2Cache can handle...
Academic researchers are interested in testing out the component they worked on.We olympia to be flexible to support those components Here are some modules that we might like to include...
For more accurate Fetch Unit behavior, speculative ops that aren't from a correct path trace provided instruction are desirable. i.e., wrong-path fetched ops (similar ops may be useful for prefetches)....
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model