riscv-perf-model
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riscv-software-src
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Hi, Thanks for uploading the .clang-format file. I tried applying the .clang-format to the files in this repo but it modifies all the files. For e.g. ``` diff --git a/core/Decode.cpp...
* Add ISA support to Mavis * Add ISA Olympia extension (json files)
Add an interconnect model for Olympia Detailed requirements TBD
While olympia already has a simple memory system, it would be good to connect it to the gem5 memory system (ruby / m5) Technical Details: TBD
The Sparta modeling framework has the beginnings of python support, although not full fleshed out. This project entails two endeavors: 1. Resurrect the python support in sparcians/map/sparta 2. Have a...
Develop replacement policies: random, LRU, TreePLRU using Sparta for various caches in Olympia. Add a documentation on how to add more complicated replacement policies.
This GH issue is a starting point, or set of tasks, to add more functionality to Olympia based on what exists in the open-source community. Those tasks are: - [...
As the model grows in size/usefulness each unit should really be in its own directory coupled with specific unit testing.
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model