cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description After setting the toolchain as indicated in util/gcc-toolchain-builder/README.md, and...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description `stall_instr_fetch` signal in `core/id_stage.sv` will not be driven if...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description According to RISC-V ISA specification, for RV32, the bit...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description This issue can be encountered in most tests in...
Currently the Camel style of parameters is not homogeneous. Need to fix it. Some examples: - XF16ALT should be renamed XF16Alt ? - RVZCB should be renamed RVZcb ? -...
TIME and TIMEH CSRs are not implemented in csr_regfile.sv.
### Task Description read_access_exception is by default set to zero in RTL. When CSR is unimplemented, it is set to one. This is costy in term og gate count. ...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Spyglass detects the presence of 33 latches in csr_regfile.sv....
Several feedbacks from 65x CSR document https://docs.openhwgroup.org/projects/cva6-user-manual/04_cv32a65x/design/source/CSRs.html - exception information need ot be added: when exception will be generated ? - Upper PMP CSR are ROCST zero - PMPCfg have...
### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description To ensure a good verification of the CVXIF 1.0.0...