Add a quick way to instantiate simple external SystemVerilog modules.

[mkorbel1]

Motivation

A lot of the time, someone may want to instantiate a SystemVerilog module without creating a new class definition or defining any internal behaviors. In these cases, you could imagine something where a simple function call instantiates an arbitrary SystemVerilog module.

Desired solution

A function (maybe a static function on ExternalSystemVerilogModule?) which accepts arguments for input ports, output ports, definition name, and parameters, and creates an instance of a that module appropriately.

Alternatives considered

No response

Additional details

No response