Allow `SynthBuilder` to accept multiple `Module`s.

[mkorbel1]

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Motivation

Sometimes there's a bunch of different independent hierarchies that we want to generate SystemVerilog for. If we generate them with independent SynthBuilders, then any shared sub-modules may be declared with the same definition name, causing issues building all them together.

Desired solution

Make it possible to pass multiple independent top-level Modules to a SynthBuilder to generate code that is uniquified properly across all of them.

Alternatives considered

No response

Additional details

No response