amaranth

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Code duplication when using a Value multiple times

2

Take the following Amaranth code: ```python class X(Elaboratable): def __init__(self): self.i = Signal(8) self.o = Signal(8) def elaborate(self, platform): m = Module() v = self.i + self.i m.d.comb += self.o.eq(v...

tilk

GTKW files with signal groups

8

For debugging complex circuits, it's useful to have the signal traces grouped according to their function. The popular _gtkwave_ tool supports this, as does the `GTKWSave` class from the `vcd`...

tilk

Add `processes` variable to `main_runner`

1

It would be nice to pass processes for simulation to the main runner. Maybe change the function signature to ```python def main_runner(parser, args, design, platform=None, name="top", ports=(), ports=(), processes=()): ......

cyber-murmel

Suggestion: DomainRenamer taking ClockDomains

4

I hate repeating strings, because typos happen. And with the global-by-default of clock domains, typos can hit something existing. So it would be nice that where a DomainRenamer takes the...

galibert

r_data is undefined after a simultaneous write to an empty AsyncFIFO

2

**Issue by [whitequark](https://github.com/whitequark)** _Friday Sep 20, 2019 at 20:02 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/217_ ---- The behavior of a dual port block RAM with read and write ports in different...

nmigen-issue-migration

**Issue by [whitequark](https://github.com/whitequark)** _Friday Sep 20, 2019 at 20:13 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/218_ ---- Due to what is arguably a bug in the Xilinx toolchain (since it synthesizes perfectly...

nmigen-issue-migration

Simulations for code that uses Platform

13

**Issue by [zignig](https://github.com/zignig)** _Tuesday Jun 25, 2019 at 00:21 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/108_ ---- Platform example ( simplified version of _blinky ) , fails to simulate. Minimal example of...

nmigen-issue-migration

Simulator with non-passive sync process and no clock added runs indefinitely without emitting a warning

2

Take the following example, some basic synchronous logic and an even more basic sync process for the simulator: ```py from nmigen import * from nmigen.back.pysim import * class Design(Elaboratable): def...

the6p4c

With both of our banner features (async testbenches and minimal streams) having undergone enough of a design process to have an RFC, it is time to decide on the final...

whitequark

- RFC PR: amaranth-lang/rfcs#56 - Implementation PR: TODO

wanda-phi