Vivado transparent memory issue

[piotro888]

Hello, (this is not directly an Amaranth issue, but I think it is worth noting / documenting here)

When generating Verilog code from Amaranth, Vivado fails to recognize read ports with transparency.

According to Horrible hack alert :) https://github.com/amaranth-lang/amaranth/blob/fd41201e20592f412b15fd33fd29a9eb36899c69/amaranth/back/rtlil.py#L1067 , I verified that Yosys generates the "old" code pattern with register at address port, that should be more compatible, but (in new versions?) Vivado fails handle it correctly.

It emits warning The block RAM may get collision error if read and write address collide and leads to non-functional gateware. Fix is to add (* rw_addr_collision = "yes" *) attribute for memories. Without it, the default behaviour is design writes to the same address it is reading from, the RAM output is unpredictable. Warnings are not emitted for non-transparent ports.

Should it be reported to yosys?

Tested on Vivado 2024.2, Amaranth 0.5.3

[whitequark]

Yeah, I would say it should be.