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A modern hardware definition language and toolchain based on Python

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When helping someone out with something involving Amaranth, I noticed that the latest main does not generate proper constraints for LVDS `DiffPairs`, causing place and route to fail due to...

bug

**Issue by [whitequark](https://github.com/whitequark)** _Tuesday Jun 11, 2019 at 04:09 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/98_ ---- This is solely blocked on Yosys issue yosyshq/yosys#726. It's in my queue for some time,...

improvement
upstream
backend:verilog

- RFC PR: https://github.com/amaranth-lang/rfcs/pull/69 - Implementation PR: N/A - Backport PR (to 0.5.1): N/A

feature

- RFC PR: https://github.com/amaranth-lang/rfcs/pull/52 - Implementation PR: TODO

feature

This for example does not work: ```python class BitSerializer(wiring.Component): def __init__(self, *, width, length): self._length = length super().__init__({ "shift": In(1), "stream": In(stream.Signature(data.StructLayout({ "o": data.ArrayLayout(width, length), "oe": 1 })), init={"payload": {"oe":...

improvement

You get messages like: ``` amaranth.hdl._ir.DriverConflict: Bit 0 of I/O port (io-port port_a_5__io__io) used twice, at /home/whitequark/Projects/glasgow/software/.venv/lib/python3.12/site-packages/amaranth/vendor/_siliconblue.py:546 and /home/whitequark/Projects/glasgow/software/.venv/lib/python3.12/site-packages/amaranth/vendor/_siliconblue.py:546 ``` It's not *completely* useless but 2/3 of the information says...

bug

For example, look at this assertion: ``` AssertionError: (cycle 0) Const(StructLayout({'port': StructLayout({'io0': StructLayout({'o': 1, 'oe': 1}), 'io1': StructLayout({'o': 1, 'oe': 1}), 'io2': StructLayout({'o': 1, 'oe': 1}), 'io3': StructLayout({'o': 1, 'oe':...

bug

Modules have a ".domain" field [used primarily for reading back domains by name, usually aliased from `m.d`] and a ".domains" field [a list which is added to to define new...

improvement