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A modern hardware definition language and toolchain based on Python

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Hello, Following our [discussion](https://github.com/amaranth-lang/amaranth/discussions/1372) on the amaranth-lang/amaranth repository, we reached out to CologneChip and requested a modification to their constraint files. Specifically, they made it possible to `Net` instead of...

- RFC PR: https://github.com/amaranth-lang/rfcs/pull/66 - Implementation PR: https://github.com/amaranth-lang/amaranth/pull/1461 - Documentation PR: N/A - Removal of deprecation PR: N/A

feature

Rendered document: ![image](https://github.com/user-attachments/assets/f6544209-6c20-441d-bf7e-7e865cbdc2b2)

In the example code the condition `done & self.stream.valid & ~self.stream.ready` is not sufficient to cause the payload to be discarded. That is because the done bit remains high. In...

Here's the rendered doc: ![image](https://github.com/user-attachments/assets/27e0f68b-2968-42b8-a56a-e24c52a86960)

Clarify where View value-likes can/can't be used like plain values

Hello, Creating instances to utilize 3rd party verilog/il modules was going rather well up to the point where one of them needed access to the raw pin, as it was...

improvement

Right now this is only possible when creating a `Resource`; however, there are many attributes (e.g. `SLEW_RATE`) which should be configured by the I/O component rather than the toplevel or...

feature
meta:needs-rfc

This removes the last major source of mutability in the core HDL, and makes it possible to use the same component hierarchy to build several bitstreams with different attributes without...

feature
meta:needs-rfc