amaranth

amaranth copied to clipboard

Make it possible for generators to simulate combinatorial logic

1

**Issue by [nakengelhardt](https://github.com/nakengelhardt)** _Tuesday Dec 18, 2018 at 05:24 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/11_ ---- Sometimes I want to use generators to build a simulation model of some module. In...

nmigen-issue-migration

Better diagnostics for undefined domain usage

1

When an undefined domain is used, nmigen issues an appropriate error, but does not specify the source line that triggered the error. Take the following example: ```python #!/usr/bin/env python from...

matthuszagh

As mentioned in a source code TODO, properly doing model equivalence checking on the AsyncFIFO requires using Yosys' multiclock formal support. Currently we check that it meets the FIFOContractSpec in...

awygle

ASIC support tracking issue

9

**Issue by [whitequark](https://github.com/whitequark)** _Thursday Aug 22, 2019 at 21:49 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/184_ ---- A number of people have expressed a desire to use nMigen for ASIC design. This...

nmigen-issue-migration

pysim: Throw Error or Warning on writing to non-port variable

1

As a beginner, this tripped me up: I was changing a Signal's value both in the module's internal logic and in my sync process during simulation, and wondering why I...

mszep

Replace use of _reset with _init in Xilinx platform.

3

This looks like an oversight, when _reset was replaced with _init in FFSynchronizer.

bl0x

Document I/O buffer library

1

[Rendered](https://whitequark.github.io/amaranth/docs/document-io/stdlib/io.html)

whitequark

While converting some testbenches from generator-based to `async`-based for [pytest-amaranth-sim](https://github.com/cr1901/pytest-amaranth-sim), I accidentally forgot to remove a `yield` on one of them: ```python @pytest.fixture(params=[pytest.param(MulTbArgs())], ids=mul_tb_id) def mul_tb(mod, request): """The multiplier testbench...

cr1901

A tutorial

2

**Issue by [RobertBaruch](https://github.com/RobertBaruch)** _Saturday Oct 12, 2019 at 14:36 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/247_ ---- Just leaving [this here](https://github.com/RobertBaruch/nmigen-tutorial). Please feel free to point out any errors, inconsistencies, nonsense, or...

nmigen-issue-migration

Implement a sanitizer for memory port combinations

5

**Issue by [whitequark](https://github.com/whitequark)** _Friday Dec 21, 2018 at 06:38 GMT_ _Originally opened as https://github.com/m-labs/nmigen/issues/12_ ---- There are a lot of possible combinations of memory ports and many of them are...

nmigen-issue-migration