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Roadmap to Amaranth 0.5
With both of our banner features (async testbenches and minimal streams) having undergone enough of a design process to have an RFC, it is time to decide on the final scope of the Amaranth 0.5 release. We have a milestone; this issue however provides more context.
Release blockers
All tasks from this list must be completed before Amaranth 0.5.0 is released.
RFCs:
- https://github.com/amaranth-lang/rfcs/pull/61
- https://github.com/amaranth-lang/rfcs/pull/59
- https://github.com/amaranth-lang/rfcs/pull/58
- https://github.com/amaranth-lang/rfcs/pull/62
- https://github.com/amaranth-lang/rfcs/pull/65
- https://github.com/amaranth-lang/rfcs/pull/63
- https://github.com/amaranth-lang/rfcs/pull/64
Features:
- Async testbenches (RFC 36, https://github.com/amaranth-lang/amaranth/issues/1213)
- Banner feature.
- Enables simulation helper functions for FIFOs and streams.
- Remaining work:
- [x] Implementation
- [ ] Guide level documentation for
amaranth.sim - [ ] Reference documentation for
amaranth.sim
- Streams (RFC 61, https://github.com/amaranth-lang/amaranth/issues/1244)
- Banner feature.
- Enables standard I/O and SoC interfacing.
- Remaining work:
- [x] Implementation
- [ ] Guide level documentation
- [ ] Reference documentation
- New
lib.io(RFC 55, https://github.com/amaranth-lang/amaranth/issues/1210)- Enables adding peripherals to standard I/O library.
- Remaining work:
- [x] Platform overrides for each platform
- [x] Guide level documentation
- [x] Reference documentation
- Component metadata (RFC 30, https://github.com/amaranth-lang/amaranth/issues/1047)
- Enables export of SoC memory maps.
- Remaining work:
- [x] Bug where
.array()on members is ignored - [x] Guide level documentation
- [x] Reference documentation
- [x] Bug where
- Removing upwards propagation of clock domains (RFC 59, https://github.com/amaranth-lang/amaranth/issues/1242)
- Necessary for clock domain rework planned for Amaranth 0.6.
- Remaining work:
- [x] Implementation
Printstatement and string formatting (RFC 50, https://github.com/amaranth-lang/amaranth/issues/1186)- Enables improved debugging and symbolic display of complex data structures in waveform viewer.
- Remaining work:
- [x] Extend Yosys with more format specifiers: YosysHQ/yosys#4301
- [x] Expand RTLIL backend to use extended format specifiers
- [x] Bump amaranth-yosys package version (after Yosys release)
- [x] Bump Yosys version requirement (after Yosys release)
- Move
hdl.Memorytolib.Memory(RFC 45, https://github.com/amaranth-lang/amaranth/issues/1083)- Enables
Memoryto interoperate withlib.wiring,lib.data - Remaining work:
- [x] Renaming
r_ports,w_portsaccessors for consistency - [x] Using correct (flipped) members in port signatures
- [x] Guide level documentation
- [x] Reference documentation
- [x] Renaming
- Enables
- Add
MemoryDatato replaceMemoryIdentity(RFC 62, https://github.com/amaranth-lang/amaranth/issues/1241)- Enables an improved testing and simulation workflow.
- Remaining work:
- [x] Implementation
- [x] Updating documentation
- Add format hook for
ValueCastable(RFC 58, https://github.com/amaranth-lang/amaranth/issues/1243)- Enables printing of custom value-castables.
- Remaining work:
- [x] Implementation
- [x] Reference documentation
- Add (public) hook for describing aggregate value representation (RFC 65, https://github.com/amaranth-lang/amaranth/issues/1293)
- Technical debt from Amaranth 0.4: forbidden coupling of
libwith privatehdlinterfaces. - Remaining work:
- [x] RFC
- [x] Implementation
- [ ] Reference documentation (if
amaranth.hdl.Formathas reference docs for 0.5)
- Technical debt from Amaranth 0.4: forbidden coupling of
- Signals with private names (https://github.com/amaranth-lang/amaranth/issues/1223)
- Technical debt from FSM rework in Amaranth 0.5: public exposure of internal
fsm_ongoing_STATEsignals. - Remaining work:
- [x] Implementation
- [ ] Documentation (if
amaranth.hdl.Signalhas reference docs for 0.5)
- Technical debt from FSM rework in Amaranth 0.5: public exposure of internal
- Deprecating
lib.coding(RFC 63, https://github.com/amaranth-lang/amaranth/issues/1292)- Removes a module no longer good enough by our standards.
- Remaining work:
- [x] Implementation
Improvements:
- EnumMeta renaming (https://github.com/amaranth-lang/amaranth/issues/1073)
- Required for compatibility with Python 3.11.
- Remaining work:
- [x] Implementation
- RTLIL backend refactor (https://github.com/amaranth-lang/amaranth/issues/1100)
- Required to land #1152, which is a fix for #1148.
- Remaining work:
- [x] Implementation
- Better error for
platform.add_clock_constraint(ClockSignal())(https://github.com/amaranth-lang/amaranth/issues/542)- Common mistake, open for 4 years.
- Remaining work:
- [x] Implementation
Regressions and problems:
- Quartus DSP inference (https://github.com/amaranth-lang/amaranth/issues/1148)
- Remaining work:
- [x] Testing
- Remaining work:
- True dual-port BRAM inference with Yosys (https://github.com/amaranth-lang/amaranth/issues/1011)
- Remaining work:
- [x] Investigation
- [x] Addressing
- Remaining work:
- Empty submodule name (https://github.com/amaranth-lang/amaranth/issues/1209)
- Remaining work:
- [ ] Implementation
- Remaining work:
- Continuous assignment to Verilog
reg(https://github.com/amaranth-lang/amaranth/issues/717)- Remaining work:
- [x] Implementation
- [x] Yosys dependency bump
- Remaining work:
Signal.likefor shape-castables (https://github.com/amaranth-lang/amaranth/issues/1285)- Remaining work:
- [x] Implementation
- Remaining work:
- Detection of combinational loops (https://github.com/amaranth-lang/amaranth/issues/704)
- Remaining work:
- [x] Implementation
- Remaining work:
- Domain handling in
lib.io(https://github.com/amaranth-lang/amaranth/pull/1347)- Remaining work:
- [x] Design
- [x] Implementation review
- Remaining work:
Nice-to-haves
Whichever tasks from this list are complete by the time all of the blockers are complete get included in Amaranth 0.5; the rest are included in Amaranth 0.6 or later.
RFCs:
- https://github.com/amaranth-lang/rfcs/pull/52
- https://github.com/amaranth-lang/rfcs/pull/41
Features:
- Structured source locations (https://github.com/amaranth-lang/amaranth/issues/1131)
- Enables improved integration with CXXRTL protocol debuggers.
- Remaining work:
- [ ] Design
- [ ] Implementation
- [ ] Testing
- Lattice Nexus platform (https://github.com/amaranth-lang/amaranth/pull/759)
- Enables support for a new FPGA family.
- Remaining work:
- [x] Validation on a Nexus developer board by @whitequark
- Expanded
.gtkwgeneration for the simulator (https://github.com/amaranth-lang/amaranth/issues/764)- Enables easier debugging of complex designs.
- Remaining work:
- [ ] Implementation
Choice(unmerged RFC 52, N/A)- Improves orthogonality of base language.
- Remaining work:
- [ ] Implemenation
- [ ] Guide level documentation
- [ ] Reference documentation
Improvements:
- Reference documentation for all of
amaranth.hdl(https://github.com/amaranth-lang/amaranth/issues/785)- Required for credibility of Amaranth as a production-grade platform.
- Guide level documentation covers enouugh ground to make this a nice-to-have rather than a blocker.
- Remaining work:
- [x]
Value.__getitem__ - [x]
Value.matches - [ ]
Const - [ ]
C - [ ]
Mux - [ ]
Cat - [ ]
Signal - [ ]
ClockSignal - [ ]
ResetSignal - [ ]
Array - [ ]
Format - [ ]
Statement(?) - [ ]
Assign(?) - [ ]
Print - [ ]
Assert - [ ]
IOValue - [ ]
IOPort
- [x]
- Clarify purpose of
.bool()vs.any()(https://github.com/amaranth-lang/amaranth/issues/1219)- Confusing to newcomers.
- Remaining work:
- [x] Update guide level documentation
- [x] Update reference documentation
- Clarify semantics of
.implies()(https://github.com/amaranth-lang/amaranth/issues/1239)- Potentially very confusing semantics
- Remaining work:
- [x] Decide on new semantics
- [x] Implement new semantics
- [x] If operator is kept, update guide level documentation
- [x] If operator is kept, update reference level documentation
- Fix TestPyPI upload (https://github.com/amaranth-lang/amaranth/issues/1229)
- Necessary to have HEAD on playground.
- Remaining work:
- [x] Implement PDM backend version hook
- [x] Test that uploads work