Memory with async read ports can synthesize to a BRAM on Xilinx platforms

[nmigen-issue-migration]

Issue by whitequark Friday Sep 20, 2019 at 20:13 GMT Originally opened as https://github.com/m-labs/nmigen/issues/218

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Due to what is arguably a bug in the Xilinx toolchain (since it synthesizes perfectly well-formed behavioral Verilog to something that has different behavior), any Memory with an asynchronous read port (often a SyncFIFO) can synthesize to a BRAM in an unpredictable way. To avoid this, a platform-specific pass should insert an attribute for any memory with asynchronous read ports that makes sure it ends up as distributed RAM.

@nakengelhardt tried to fix this in oMigen in https://github.com/m-labs/migen/pull/105, but oMigen does not have the infrastructure required to fix this properly.