Language wide simulation test case support

[JulianKemmerer]

Barbossa404 on Discord brought up how running tests/testbenches should be as easy as possible

Consider for typical Verilog or VHDL you can have a setup like:

$ my_simulator my_verilog_testbench.v

simulator starts up, runs sim, logs waveforms, exits The built in Verilog like $finish, error etc kind of things are what causes the sim to fail or pass

PipelineC can sometimes be compiled as C, use any HDL simulator, and might even drive cocotb. It would be great to have a unified way of running the pipelinec tool to run a simulation, log waveforms, get results etc.

Closest right now is Verilator support --main_cpp argument to compile and run a certain .cpp file with your pipelinec my_file.c --sim --verilator.