Veripool API Bot

Support full UVM -cc code generation

48

This issue tracks the remaining subissues that must be fixed before UVM can be converted to C++. This first comment is updated periodically to summarize the most recent state. **Note...

Support bind statements within generate blocks

7

--- Author Name: **Dan Petrisko** (@dpetrisko) Original Redmine Issue: 1501 from https://www.veripool.org --- A bind statement within a generate if, if the generate if evaluates to false, should not bind....

Support primitive instantiations (UDPs)

13

--- Author Name: **Alex Solomatnikov** Original Redmine Issue: 468 from https://www.veripool.org Original Date: 2012-03-23 --- Primitive definition: ``` primitive PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier); input D; input...

verilator does not detect if block name is used twice

2

--- Author Name: **Alex Solomatnikov** Original Redmine Issue: 485 from https://www.veripool.org Original Date: 2012-04-19 --- Code: ``` always_comb begin integer q_ind; for( q_ind=0; q_ind

Improve internals of inliner

2

--- Author Name: **Wilson Snyder** (@wsnyder) Original Redmine Issue: 1539 from https://www.veripool.org --- Feature tracking bug. The current module inliner code works by operating on modules before the complete scoped...

alignment and indentation issue with import and "=" for localparam

3

--- Author Name: **Enzo Chi** Original Redmine Issue: 1272 from https://www.veripool.org --- I am using verilog-mode from commit "c579c46" and set "verilog-auto-lineup" to "all" Example code: ``` module alignment_test import...

SystemVerilog interface indentation in module declaration

2

--- Author Name: **Clarke Watson** Original Redmine Issue: 1446 from https://www.veripool.org --- Hi, Thanks for creating and maintaining verilog-mode. It is awesome! I am having trouble getting SystemVerilog interfaces inside...

Using ':' for end-lable instread of "// SysteVerilog

9

--- Author Name: **Greg Hilton** Original Redmine Issue: 956 from https://www.veripool.org --- Currently verilog-mode will place a end comment for functions, tasks, modules, primitives, classes, etc. Instead of "//" SystemVerilog's...

Expand AUTOINST default values for parameters

4

--- Author Name: **Mert Ustun** Original Redmine Issue: 1447 from https://www.veripool.org --- When I use verilog-auto-inst-param-value:t, it can successfully replace bus indexes with parameter values only if the parameter is...

AUTOLOGIC/AUTOINST for unpacked array signal input to submodule

5

--- Author Name: **David Rogoff** Original Redmine Issue: 1453 from https://www.veripool.org --- Hi Wilson. Thanks for the super-quick answer to my last question! Here's another: I have a signal like...