Veripool API Bot

Indenting/Highlighting user defined types

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--- Author Name: **Jonathan Greenlaw** Original Redmine Issue: 308 from https://www.veripool.org Original Date: 2010-12-16 --- Indenting and highlighting does not recognize user defined types as specified by the verilog-typedef-regexp variable.

Conditional event controls ("iff")

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--- Author Name: **Paul Donahue** Original Redmine Issue: 1482 from https://www.veripool.org --- Section 9.4.2.3 of IEEE 1800-2017 allows "iff" qualifiers on @ event controls. The example code in 9.4.2.3 is...

Support for /*verilator public*/ on SV structs too?

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--- Author Name: **Jonathon Donaldson** Original Redmine Issue: 860 from https://www.veripool.org Original Date: 2014-12-11 --- The recently added feature of being able to use /*verilator public*/ on SV enums is...

Support covergroup

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--- Author Name: **Alex Solomatnikov** Original Redmine Issue: 784 from https://www.veripool.org Original Date: 2014-06-10 --- Example RTL: ``` covergroup cg_forward_path_control @(posedge clk); rd_state: coverpoint {rd_cnt_not_zero, rd_deq} { illegal_bins illegal =...

--- Author Name: **Todd Strader** (@toddstrader) Original Redmine Issue: 1524 from https://www.veripool.org Original Assignee: Todd Strader (@toddstrader) --- I need to look into this more, but I believe that Verilator...

Parameter-resolved constants from interface components

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--- Author Name: **Ahmed Qureshi** Original Redmine Issue: 1593 from https://www.veripool.org --- When doing something like this: localparam MY_WIDTH = $bits({my_intf.signal1, my_intf.signal2}); We get the following error: Parameter-resolved constants must...

Preprocessor doesn't handle one case of definition substitution properly

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--- Author Name: **Topa Tota** Original Redmine Issue: 1659 from https://www.veripool.org Original Assignee: Wilson Snyder (@wsnyder) --- If you run the preprocessor on this code ``` `define test(a1,a2) ((a1) +...

Parser doesn't understand constraint implication operator ('->')

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--- Author Name: **Dave Storrar** Original Redmine Issue: 1064 from https://www.veripool.org Original Date: 2016-05-29 --- The following code produces a parsing error: ``` class testcase; rand bit [3:0] a, b;...

Raise error / warning on continous assignment to reg

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--- Author Name: **Peter Gerst** Original Redmine Issue: 1369 from https://www.veripool.org Original Assignee: Wilson Snyder (@wsnyder) --- Verilator does not throw error / warning on continuous assignment to a register....

Bad scaling, if there are nasty forests of generate statements

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--- Author Name: **John Coiner** (@jcoiner) Original Redmine Issue: 1314 from https://www.veripool.org Original Assignee: John Coiner (@jcoiner) --- This patch adds two tests: One is a tree of modules, defined...