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Expand AUTOINST default values for parameters
Author Name: Mert Ustun Original Redmine Issue: 1447 from https://www.veripool.org
When I use verilog-auto-inst-param-value:t, it can successfully replace bus indexes with parameter values only if the parameter is explicitly assigned a value during the module instantiation. In many cases, parameter values could be left as default without any explicit setting, especially if the default value is inferred from another assigned parameter.
For instance, taking the example in Issue #522,
module submod (/*AUTOARG*/
// Outputs
idx,
// Inputs
vec
);
parameter VEC_W = 32;
parameter IDX_W = $clog2(VEC_W);
input [VEC_W-1:0] vec;
output [IDX_W-1:0] idx;
endmodule
module mod;
submod #
(.VEC_W(8),
.IDX_W($clog2(VEC_W)))
submod
(/*AUTOINST*/
// Outputs
.idx (idx[($clog2(8))-1:0]),
// Inputs
.vec (vec[7:0]));
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// End:
There is no need to set IDX_W parameter during instantiation since it's same as the default assigned value. However, verilog-auto-inst-param-value will not expand the param value if the parameter value is not explicitly set during instantiation.
I actually realized my request was already there in Issue #522, at the bottom:
_My next request would be to make it work:
if IDX_W isn't passed
if IDX_W is a localparam in submod
These two conditions are very common and would be great if Verilog-mode could support parameter value expansion for these two cases.
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-28T11:05:29Z
I agree this would be useful. It will be some work as requires parsing significant information that isn't presently parsed.
Yes it would be useful. I would really like to see this implemented too. There are some parameters that should remain parameters, not localparam, but have defaults.
