AUTOLOGIC/AUTOINST for unpacked array signal input to submodule

[veripoolbot]

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Author Name: David Rogoff Original Redmine Issue: 1453 from https://www.veripool.org

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Hi Wilson.

Thanks for the super-quick answer to my last question!

Here's another:

I have a signal like this: logic [7:0] sig_a [2];

sig_a [0] 

comes from one instance of module xx and sig_a[1] from the other instance.

The full ```sig_a [2]

When I expand autos, I get this under /*AUTOLOGIC*/

  logic [0] [7:0] sig_a; // From inst_xx_0

If it's the other direction, it works fine, but it looks like AUTO prioritizes outputs of modules and gets confused.  How can I fix this without manually declaring all of these signals?

Thanks,

David

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-06-04T00:53:39Z

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Verilog-mode doesn't figure out how to deal with 2-D and up structures, it just assumes the first output is what you want. The combining code is already complicated so is unlikely to get reworked to improve this case, so you'll need to declare it manually.

[veripoolbot]

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Original Redmine Comment Author Name: David Rogoff Original Date: 2019-10-11T17:14:22Z

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Wilson, I understand you not wanting to fix this but I keep hitting this issue on huge upper-level integration modules - exactly where AUTOs are great. Have you considered making a paid version of verilog-mode to give you and other developers incentive to do some of the more difficult fixes? After years and years of relying on your code (and emacs) I'm starting to look at eclipse with plugins like DVT (which is certainly not free!).

David

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-10-18T02:24:29Z

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If you can provide some examples I'll take a look if there's some straightforward cases I can cover (gratis). Please include a reasonable number of cases in a file along with how you think they should be properly combined, including some cases that shouldn't combine. Note presently all the following are different internally so each of these need to be tested against whatever combine permutations:

reg [x:y] packed;
reg [x:y][x:y] packed2d;
reg unpacked [x:y];
reg unpacked2d [x:y][x:y];
reg [x:y] packedunpacked [x:y];
reg [x:y][x:y] unpacked2d [x:y][x:y];