Veripool API Bot

Backslash inside quotes for uvm_info/error messages

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--- Author Name: **Rajendra O** Original Redmine Issue: 1074 from https://www.veripool.org --- Hi, I observed that auto-indentation is not possible if one tries to auto-indent the uvm_info/error messages with messages...

AUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times

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--- Author Name: **Hanan Moller** Original Redmine Issue: 1019 from https://www.veripool.org --- Hello, When a wire (bus) is created due to AUTOINST + templates and then referred to using AUTOOUTPUTEVERY,...

Misalignment of labeled assertions inside if...else...

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--- Author Name: **Bernd Beuster** Original Redmine Issue: 988 from https://www.veripool.org --- verilog-version 2015-09-21-d3012e9-vpo

Consistent comment column

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--- Author Name: **Monte Becker** Original Redmine Issue: 922 from https://www.veripool.org --- Hi there: I've had a devil of a time getting comments to start in the column I'd like...

SystemVerilog class auto declaration line up

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--- Author Name: **Monte Becker** Original Redmine Issue: 920 from https://www.veripool.org --- Hi there: When creating a function or task in a class, I like to line up my declarations....

randsequence misindented

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--- Author Name: **Wilson Snyder** (@wsnyder) Original Redmine Issue: 838 from https://www.veripool.org --- Yanming Gao emails: ``` module a; randsequence(TOP) TOP: A B C D; A: seq_a; B: seq_b; C:...

Understand few defconsts

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--- Author Name: **Kaushal Modi** Original Redmine Issue: 1160 from https://www.veripool.org --- Hi, I was working on refactoring @verilog-prettify-expr@ function and I came across the @verilog-basic-complete-re@ and @verilog-complete-reg@ variables. These...

AUTOARG order with AUTOINPUT

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--- Author Name: **Shareef Jalloq** Original Redmine Issue: 962 from https://www.veripool.org Original Date: 2015-09-04 --- Hi, I'm running an older version of Verilog Perl, 3.223, so this might have been...

bus width alignment

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--- Author Name: **Alex Hornung** Original Redmine Issue: 562 from https://www.veripool.org Original Date: 2012-09-12 --- I've started using verilog-mode a few months ago and am overall quite happy with it....

verilog-pretty-expr doesn't work in latest version

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--- Author Name: **Michael Rytting** Original Redmine Issue: 447 from https://www.veripool.org Original Date: 2012-03-05 --- I have verilog-auto-lineup set to 'all, but the function doesn't line anything up. It no...