veripool
Using ':' for end-lable instread of "// SysteVerilog
Author Name: Greg Hilton Original Redmine Issue: 956 from https://www.veripool.org
Currently verilog-mode will place a end comment for functions, tasks, modules, primitives, classes, etc. Instead of "//" SystemVerilog's IEEE 1800 LRM suggests using ':'. It is not backward compatible with IEEE 1364, so maybe a
References from "IEEE Std 1800-2012":http://standards.ieee.org/getieee/1800/download/1800-2012.pdf
- A.1.2 SystemVerilog source text
- A.1.5 Configuration source text
- A.1.9 Class items
- A.2.6 Function declarations
- A.2.7 Task declarations
- A.2.10 Assertion declarations
- A.2.11 Covergroup declarations
- A.5.1 UDP declaration A.6.3 Parallel and sequential blocks A.6.11 Clocking block
Original Redmine Comment Author Name: Greg Hilton Original Date: 2015-08-11T21:44:55Z
Some how my request got submitted before I finished filling it in; and I cannot edit :(
Basically I, like an option to use the verilog-set-auto-endcomments use ':' for end-lables instead of "//". With a backward (or forward) compatable switch for users that what to strictly use IEEE 1364 syntax.
Original Redmine Comment Author Name: Alex Reed Original Date: 2015-08-12T12:39:52Z
I like this idea (and I've even thought about implementing it before...)
As you mention, this is only an IEEE 1800 syntax feature and is not backward compatible with IEEE 1364. If this were added to verilog-mode, I think it would require setting a variable (verilog-end-label-sv perhaps?) and only work if the specified buffer ends in an SV extension (verilog-sv-extensions =
Assigning to myself and setting low priority. I'll get to it eventually...
Original Redmine Comment Author Name: Alex Reed Original Date: 2016-02-19T19:32:00Z
From Kaushal Modi in www.veripool.org/issues/1038-Verilog-mode-Support-for-named-ends-Example-endclass-CLASSNAME-
Hi,
I was leaning towards getting auto named ends functionality just like the auto endcomments functionality that we have right now.
Initially my thought was to add a defvar which would use ":" instead of "//" when auto inserting the named ends (instead of named comments).
That too would only happen for these endings (as per IEEE SystemVerilog Standard 1800-2012, Section 9.3.4, pg 178):
— endchecker (see 17.2)
— endclass (see 8.3)
— endclocking (see 14.3)
— endconfig (see 33.4)
— endfunction (see 13.4)
— endgroup (see 19.2)
— endinterface (see 25.3)
— endmodule (see 23.2.1)
— endpackage (see 26.2)
— endprimitive (see 29.3)
— endprogram (see 24.3)
— endproperty (see 16.2)
— endsequence (see 16.8)
— endtask (see 13.3)
But looking at this line in the verilog-mode.el, it looks like the named ends were considered but instead of auto-updating them, lines with named ends were totally ignored.
Before I try to get a solution to auto named ends (only for the above types of endings), I was like to know the reason for that specific (unless ..) condition.
The reason I am looking into this is because I see a growing convention of using named ends instead of comments at the ends. Named ends can help catch a copy/paste mistake if the user had mismatch between the block name and end name.
Thanks.
Further review shows that the (unless ...) was added in https://github.com/veripool/verilog-mode/commit/8f6e75dc5d0627ce548f49a5b937e619ba279b79#diff-c480fc7ce25d2b23c9996dc931e5b3d9R2503 in 2004. I think it's safe to assume that this code needs to be re-evaluated.
Please, hack away and see what you can come up with! :)
Original Redmine Comment Author Name: Kaushal Modi Original Date: 2016-02-19T20:36:07Z
Cool! Any idea about that unless condition?
Original Redmine Comment Author Name: Kaushal Modi Original Date: 2016-02-21T04:53:17Z
I missed reading these lines earlier when I posted that reply:
Further review shows that the (unless ...) was added in https://github.com/veripool/verilog-mode/commit/8f6e75dc5d0627ce548f49a5b937e619ba279b79#diff-c480fc7ce25d2b23c9996dc931e5b3d9R2503 in 2004. I think it's safe to assume that this code needs to be re-evaluated. Please, hack away and see what you can come up with! :)
Alright, I'll look into the named end support.
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-11-19T13:26:53Z
Still missing feature AFAIK, perhaps someone would like to contribute a patch?
If you want a truly lazy .emacs solution that you can hook on save (or run from shell since you've already succumbed to emacs for verilog-mode), I've been converting the // the : on save:
;; Verilog hacks:
(defun verilog-fix-trailing-comments ()
"Replaces things like 'endmodule // comment' with endmodule : comment."
(interactive)
(if (string= mode-name "Verilog")
(let (pt)
(setq pt (point))
(goto-char (point-min))
(while (re-search-forward "endmodule +// +" nil t)
(replace-match "endmodule : "))
(goto-char (point-min))
(while (re-search-forward "endtask +// +" nil t)
(replace-match "endtask : "))
(goto-char (point-min))
(while (re-search-forward "endpackage +// +" nil t)
(replace-match "endpackage : "))
(goto-char (point-min))
(while (re-search-forward "endfunction +// +" nil t)
(replace-match "endfunction : "))
(goto-char pt)
)
))
Seems a good idea, pehaps you'd consider to conditionalize the code with a new variable and submit a pull request?
I'd love to, but after some back and forth with my current employer, they won't let me work on open source anything.