alignment and indentation issue with import and "=" for localparam

[veripoolbot]

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Author Name: Enzo Chi Original Redmine Issue: 1272 from https://www.veripool.org

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I am using verilog-mode from commit "c579c46" and set "verilog-auto-lineup" to "all"

Example code:

module alignment_test
import bar_pkg::*;
     import foo_pkg::*;
     #(
       parameter DATA_WIDTH = 8,
       parameter ADDR_WIDTH = 4
       )
     (
      input wire                  clk,
      input wire                  res_n,
      input wire                  valid,
      input wire [DATA_WIDHT-1:0] data_in,
      input wire [ADDR_WIDTH-1:0] addr,
      output logic                accept
      );

     localparam LP_BAR_0 = 1;
     localparam LP_BAR_100 = 100;
     localparam logic [3:0]       LP_BAR_5 = 5;

endmodule

1. The first "import" right after the module name is not indent and not aligned with the second one.
2. The local parameter names are not aligned.
3. The "=" of local parameters are not aligned.
4. It looks like the LP_BAR_5 is tried to aligned with the port list. What I think the aligned should be inside scope: {}, (), begin/end, etc

Here is the expected code:

module alignment_test
     import bar_pkg::*;
     import foo_pkg::*;
     #(
         parameter DATA_WIDTH = 8,
         parameter ADDR_WIDTH = 4
     )
     (
         input wire                  clk,
         input wire                  res_n,
         input wire                  valid,
         input wire [DATA_WIDHT-1:0] data_in,
         input wire [ADDR_WIDTH-1:0] addr,
         output logic                accept
      );

     localparam             LP_BAR_0   = 1;
     localparam             LP_BAR_100 = 100;
     localparam logic [3:0] LP_BAR_5   = 5;

endmodule

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-02-02T00:30:47Z

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I agree this isn't what's expected. Please note the indent code is mostly fixed by contributions, so there may be a long wait for a fix unless you can contribute a parch.

[vinamarora8]

https://github.com/veripool/verilog-mode/pull/1683 solves point 2 and 4

[gmlarumbe]

From #1800:

Everything indents and aligns correctly except for package imports between module identifier and parameter list. Even though this seems supported by simulators (tested in Xcelium 19.09) I do not think it would be worth the effort looking into it since package importing in the unit space and after ports list already indents correctly.

You could import your packages either in the unit space or after module ports:

import bar_pkg1::*;
import foo_pkg1::*;

module alignment_test
     #(
       parameter DATA_WIDTH = 8,
       parameter ADDR_WIDTH = 4
       )
     (
      input wire                  clk,
      input wire                  res_n,
      input wire                  valid,
      input wire [DATA_WIDHT-1:0] data_in,
      input wire [ADDR_WIDTH-1:0] addr,
      output logic                accept
      );

     import bar_pkg2::*;
     import foo_pkg2::*;

     localparam LP_BAR_0 = 1;
     localparam LP_BAR_100 = 100;
     localparam logic [3:0]       LP_BAR_5 = 5;

endmodule