vtr-verilog-to-routing

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VPR Pack: Replace hand-implemented linked lists to std::lists

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Related to PR #2084 Lists such as the ones vpr/src/base/vtr_types.cpp (line 236) might be better implemented as std::lists. Refer to https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/2084#discussion_r915061111

jmah76

Related to PR #2084 Change the C arrays in vpr/pack that get delete[] called on them to C++ vectors. > Using delete[] indicates that this is some sort of array...

jmah76

Dangling interconnect occurs when connecting a wire to a switch of type short

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#### Current Behavior For some reason, when an interconnect is specified between a wire and a wire with an arch_wire_switch of type short there are some cases when unspecified interconnect...

WhiteNinjaZ

Needed features in VTR description to represent Xilinx architecture

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#### Proposed Behaviour The following is a list of functionality that would need to be supported in VTR in order to obtain an approximate capture of the Xilinx architecture: -...

WhiteNinjaZ

Addition of switch_override feature to custom SB

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#### Description This PR allows a user to specify a switch_override within the wireconn of a custom SB. The given switch will be used to override the wire_switch of the...

WhiteNinjaZ

Fix build errors with VERBOSE

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This PR contains some general fixes #### Description The PR fixes build errors when `VERBOSE` is defined. It also fixes VPR ignoring netlist verbosity commandline option. #### Related Issue ####...

mkurc-ant

Hi to everyone. I am trying to build my own fpga architecture and I was able to make it work for a small design which contained just a multiplier and...

cristianomodesti

When I uncomment VERBOSE flag in "vpr_types.h", I can't build VPR. It seems the problem is mainly related to some parts of the placement code. I had to comment the...

amin1377

Update dead FASM specification url

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#### Description Doc update only, update FASM specification url in README #### Related Issue #### Motivation and Context Improve documentation #### How Has This Been Tested? #### Types of changes...

IanBoyanZhang

Example of Xilinx architecture description

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#### Description This PR adds an example of an approximate capture of the Xilinx architecture to VTR. #### Motivation and Context Several recent changes to VTR remain to be tested...

WhiteNinjaZ