vtr-verilog-to-routing
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verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
The router has a function that was added for the initial 3D routing (from OPINs) that checks some high-level architecture variables and decides whether or not to expand a node....
As I know, Titan benchmarks are input directly to vpr, so that skip the ACE step necessary to perform power analysis. So I can't perform power analysis directly by run_vtr_flow.py....
Close #2545. Rewrote the existing Profiling VTR section, specifically the one using GNU `gprof` tool. Added another subsection to explain how to use the Linux `perf` tool to profile VPR...
## Problem Description This issue is to report a problem in the ABC tool's output generation of BLIF files. Attached are the input BLIF file that produces the problematic output...
VTR now supports 3D devices, but the placement constraints documentation at https://docs.verilogtorouting.org/en/latest/vpr/placement_constraints/ is still 2D. #### Proposed Behaviour Update the example and documentation to 3D. Confirm the code works for...
We should have a test for this, as we have some new tags (layers) and we also are autocreating a wire segment type for 3D switch blocks. We should have...
The std::iterator class will be deprecated in C++17: - https://stackoverflow.com/questions/43268146/why-is-stditerator-deprecated In CI, the GCC 12 and CLANG 14 build show the deprecation warnings. There are other warnings in these builds,...
Merge master to openfpga feature branch. There are test failures which look like to be caused by RSA settings.
When trying to print out a large overuse report (at an early iteration) we hit the assert at [`overuse_report.cpp:474` ](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/route/overuse_report.cpp#L474). To reproduce, run `directrf` with `--max_router_iterations 10 --generate_rr_node_overuse_report on` (tested...
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Verilog to Routing -- Open Source CAD Flow for FPGA Research