Assertion 'clk_pin' failed

[cristianomodesti]

Hi to everyone. I am trying to build my own fpga architecture and I was able to make it work for a small design which contained just a multiplier and a few other logic elements. Now I am running the same flow for a bigger design starting by the specification of a vpr architecture composed only by LUTs and FFs. When I run the vpr command with the --timing_analysis off I am able to let the flow do its job and open the graphical view of the architecture, but if I enable the timing analysis (which I of course need), I get the following error:

Circuit Statistics:
  Blocks: 2440
    .input :     135
    .latch :     293
    .output:     111
    0-LUT  :      54
    6-LUT  :    1847
  Nets  : 2329
    Avg Fanout:     2.8
    Max Fanout:   213.0
    Min Fanout:     1.0
  Netlist Clocks: 0
# Build Timing Graph

[...]/timing_graph_builder.cpp:251 add_block_to_timing_graph: Assertion 'clk_pin' failed.

I am not 100% sure about that Netlist Clocks: 0 and what 0-LUT stands for. The architecture xml file is the following:

<architecture>
  <models>
    <model name="io">
      <input_ports>
        <port name="outpad"/>
      </input_ports>
      <output_ports>
        <port name="inpad"/>
      </output_ports>
    </model>
  </models>

  <tiles>
    <tile name="io" capacity="8" area="0">
      <equivalent_sites>
        <site pb_type="io"/>
      </equivalent_sites>
      <input name="outpad" num_pins="1"/>
      <output name="inpad" num_pins="1"/>
      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
      <pinlocations pattern="custom">
        <loc side="left">io.outpad io.inpad</loc>
        <loc side="top">io.outpad io.inpad</loc>
        <loc side="right">io.outpad io.inpad</loc>
        <loc side="bottom">io.outpad io.inpad</loc>
      </pinlocations>
    </tile>

    <tile name="clb" area="53894">
      <equivalent_sites>
        <site pb_type="clb"/>
      </equivalent_sites>
      <input name="I" num_pins="30" equivalent="full"/> 
      <output name="O" num_pins="20" equivalent="instance"/> 
      <clock name="clk" num_pins="1"/>
      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
      <pinlocations pattern="custom">
        <loc side="left">clb.clk</loc>
        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
        <loc side="bottom">clb.O[19:10] clb.I[29:20]</loc>
      </pinlocations>
    </tile>
  </tiles>

  <layout tileable="false">
    <fixed_layout name="18x18" width="19" height="19">
      <perimeter type="io" priority="100"/>
      <corners type="EMPTY" priority="101"/>
      <fill type="clb" priority="10"/>
    </fixed_layout>
  </layout>

   ...

  <pb_type name="clb">
      <input name="I" num_pins="30" equivalent="full"/> 
      <output name="O" num_pins="20" equivalent="instance"/> 
      <clock name="clk" num_pins="1"/>

			<pb_type name="fle" num_pb="10">
				<input name="in" num_pins="6"/>
				<output name="out" num_pins="2"/>
				<clock name="clk" num_pins="1"/>
				<!-- 1 x 6-LUT -->
			      <pb_type name="ble6" num_pb="1">
				      <input name="in" num_pins="6"/>
				      <output name="out" num_pins="1"/>
				      <clock name="clk" num_pins="1"/>
				      <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
					      <input name="in" num_pins="6" port_class="lut_in"/>
					      <output name="out" num_pins="1" port_class="lut_out"/>
					      <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
						      261e-12
						      261e-12
						      261e-12
						      261e-12
						      261e-12
						      261e-12
					      </delay_matrix>
				      </pb_type>
				      <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
					      <input name="D" num_pins="1" port_class="D"/>
					      <output name="Q" num_pins="1" port_class="Q"/>
					      <clock name="clk" num_pins="1" port_class="clock"/>
					      <T_setup value="66e-12" port="ff.D" clock="clk"/>
					      <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
				      </pb_type>
				      <interconnect>
					      <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
					      <direct name="direct2" input="lut6.out" output="ff.D">
						      <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
					      </direct>
					      <direct name="direct3" input="ble6.clk" output="ff.clk"/>
					      <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
						      <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
						      <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
					      </mux>
				      </interconnect>
			      </pb_type>
			      <interconnect>
				      <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
				      <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
				      <direct name="direct3" input="fle.clk" output="ble6.clk"/>
			      </interconnect>
			</pb_type>
			
      <interconnect>
        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
          <delay_constant max="8.044000e-11" in_port="clb.I" out_port="fle[9:0].in"/>
          <delay_constant max="7.354000e-11" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
        </complete>
        <complete name="clks" input="clb.clk" output="fle[9:0].clk"/>
        <complete name="clbouts" input="fle[9:0].out" output="clb.O"/>				
      </interconnect>
      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
      <pinlocations pattern="spread"/>
    </pb_type>
  </complexblocklist>
</architecture>

and the .blif file I am usign to run vpr is generated thanks to YOSYS. Does anyone have an idea about where that error can come from, or a hint about how to resolve it? Thank you so much