vtr-verilog-to-routing
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verilog-to-routing
Example of Xilinx architecture description
Description
This PR adds an example of an approximate capture of the Xilinx architecture to VTR.
Motivation and Context
Several recent changes to VTR remain to be tested in the reg_tests. This PR attempts to remedy this as well as to provide an example of a simplified Xilinx architecture. The plan is to continue adding descriptions in this file that test the functionality of new features (i.e. diagonal wires, partial crossbars, different architecture width/height, etc.) For now we only provide the description for a simplified CLB that matches the Xilinx arch as well as correct wire distributions/lengths in the horizontal/vertical directions (a feature newly added by PR #1883). Care has been taken to only include functionality in this PR that is fully supported by the current flow. In cases where functionality is currently lacking, comments are present.
Types of changes
- [ ] Bug fix (change which fixes an issue)
- [x] New feature (change which adds functionality)
- [ ] Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
- [ ] My change requires a change to the documentation
- [ ] I have updated the documentation accordingly
- [x] I have added tests to cover my changes
- [ ] All new and existing tests passed
