vtr-verilog-to-routing

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Unable to Describe Diagonal Wires with Current VPR architecture description

4

#### Current Behaviour Several current FPGA's utilize diagonal routing in their architectures (specifically Xilinx parts). Currently, VPR has no way to implement this functionality. The proposal has been made that...

WhiteNinjaZ

https://docs.verilogtorouting.org/en/latest/vtr/python_libs/vtr/ has the skeleton of documentation for this library, but only the headings are there. #### Proposed Behaviour Complete the documentation #### Context Our flow scripts are pretty complex (and...

vaughnbetz

--graphics command doesn't seem to work

1

Trying to use --graphics command on example runs in the document, but command gives error #### Expected Behaviour Should save a graphics file #### Current Behaviour Command gives error ####...

sildipankar

Supporting rr_graphs with non-identical horizontal and vertical channels in the Serializer

1

#### Context #1883 enables the rr_graph to model different horizontal and vertical channels. As a follow up to this feature, the seralizer should also able to support rr_graphs generated after...

ArashAhmadian

Request: Fail if timing is not met

7

The user should know when their implementation does not meet their stated timing goal. It is not clear from vpr when this is the case. #### Proposed Behaviour Perhaps by...

tcal-x

Support SystemVerilog using Surelog parser

6

We should be able to handle SystemVerilog input using the Surelog front-end for yosys. * Add a simple regression test to check end-to-end flow. * Update documentation to explain how...

jgoeders

I have noticed that the current VPR implementation does not allow for wires to terminate without a fan out/fan in from a switch block. This can be an issue if...

WhiteNinjaZ

[Odin] How to trace the fail in odin.out file?

1

Hi, The odin II process fails without generating any .blif file. In the Odin.out file, I am trying to trace back where the problem is. The output file looks like...

Sun1927

#### Description ##### DEPENDS ON #1999 (I will rebase this branch to exclude commits from #1999 once it gets merged). Parse XDC placement constraints using TCL interpreter. * `libtclcpp` -...

kboronski-ant

Odin: wire is a net type and cannot be on left in always block

5

#### Expected Behaviour An error should occur when a net type is assigned a value in an always block. Only data types are allowed for that. ex reg #### Current...

emacdo12