vtr-verilog-to-routing
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verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Hello, I'm a BYU student working with Jeff Goeders, working on routing specifically. Currently any added segments listed in the architecture occur in both horizontal and vertical routing channels. Newer...
Hi, I am a BYU CCL student working with Jeff Goeders and have been working on an improvement to the detailed routing so that we can specify different channel widths...
#define guarded change to modify router loop exit behavior (not enabled by default). Instead of exiting at max_router_iterations, if IGNORE_ITERATION_LIMIT_HEAP_PUSH_FACTOR is defined, the router will continue to run iterations if...
- Add the scaled delay from the "koios_3d" benchmark into the 3D SIV-like architecture. The inter-die delay is calculated by multiplying the delay of the L4 segment by the ratio...
In this PR, the ".bin" extension has been added as an acceptable file extension for the router lookahead file.
In previous commits of VPR, a file extension for the router lookahead such as ".bin" could be used without issue. In the most recent commit of VPR, an assertion is...
The current expansion pruning in the router uses the drive point of every `RRNode` (`(xlow ,ylow)` for non-directional nodes). This check is inside a hot loop (in `connection_router.cpp`), so there...
When attempting to execute run-flat on Koios benchmarks using VPR, the software crashes.
#### Description #### Related Issue #### Motivation and Context #### How Has This Been Tested? #### Types of changes - [x] Bug fix (change which fixes an issue) - [...
Current find_new_root_atom_for_chain assumes that an atom without a driver is the root of a chain, and so all non-chain luts are considered trivial length-1 chains. This fix permits a driverless...
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Verilog to Routing -- Open Source CAD Flow for FPGA Research