vtr-verilog-to-routing
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verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Adding a link to the EZGL documentation in the VPR UI editing tutorial in VTR Docs
The auto-layout process increases device size to ensure that the design fits. It only compares the number of block locations of each type with the number of blocks in design...
#### Expected Behaviour When a BRAM/memory is inferred from behavioral Verilog code, both flows - ODIN only and ODIN+Yosys - should result in the same hardware. #### Current Behaviour There...
#### Expected Behaviour According to the latest documentation on the [VTR benchmark](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/bec02d3022789fc0b6c44fdf207ef2141d99b461/doc/src/vtr/benchmarks.rst#vtr-benchmarks), there should be pre-synthetized designs at `$VTR_ROOT/vtr_flow/benchmarks/vtr_benchmarks_blif` #### Current Behaviour The directory is not present at the current...
Hello, VPR throws an error message when it tries to route the ISPD benchmarks provided in VTR. The architecture used is [ultrascale_ispd.xml](https://raw.githubusercontent.com/verilog-to-routing/vtr-verilog-to-routing/master/vtr_flow/arch/ispd/ultrascale_ispd.xml). #### Expected Behaviour VPR should successfully route the...
When using yosys+odin with the 'paj_boundtop_hierarchy_no_mem' verilog input file, with or without arch file, everything looks fine and the verilog file is being elaborated and partial mapped successfuly, however if...
When building vtr, not able to enable graphics. Warning message: "EasyGL: Failed to find required X11 library (on debian/ubuntu try 'sudo apt-get install libx11-dev' to install)". Installing libx11-dev not solving...
The regression test vtr_timing_update_diff_titan often fails when running on a local machine (specifically wintermute). So far, the test has not failed on the CI, although it has been running continuously...
Right now the script infrastructure for regtests, running suites of designs etc. in vtr assumes each benchmark consists of one file. We're slightly weakening that by allowing .vh include files,...
ifdef-endif seems to not be recongized properly by Odin. The adder circuits located [here](https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog) are syntactically correct however Odin marks the output `sum` as undriven. #### Expected Behaviour Should synthesize...
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Verilog to Routing -- Open Source CAD Flow for FPGA Research