vtr-verilog-to-routing

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VPR Placer runtime issue when all design clusters have fixed locations

6

VPR Placer has a large runtime when all the input design clusters have fixed locations. #### Expected Behaviour When all clusters are fixed, VPR's place stage should complete very fast...

rachelselinar

Typo

4

#### Description Just a typo. #### Related Issue #### Motivation and Context #### How Has This Been Tested? #### Types of changes - [ ] Bug fix (change which fixes...

stef9998

Ability to act as a server using a socket communication link, handle critical path list requests, and highlight certain critical path requests

1

[vpr_it1_pullrequest.pdf](https://github.com/verilog-to-routing/vtr-verilog-to-routing/files/14128999/vpr_it1_pullrequest.pdf) #### Description #### Related Issue #### Motivation and Context #### How Has This Been Tested? #### Types of changes - [ ] Bug fix (change which fixes an issue)...

w0lek

Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `01cac90` to `1078e7e`. Commits 1078e7e Fix clang-tidy bugprone-chained-comparison warnings 79205da Fix typo in release notes for v3.5.2 658acee Run tests on all cores in GHA jobs 05e10df...

dependabot[bot]

fixed sdc file copy and parmys abs path to temp folder issue

5

This PR resolves issue #2420 and provides a work around to #2302. #### Description The run_vtr_flow.py script was modified to properly copy a specified sdc file into a temp directory...

WhiteNinjaZ

Updating k6_N10_40nm.xml arch and adding a sparse version; making more user friendly for teaching use

1

Updating k6_N10_40nm.xml and adding k6_N10_sparse_crossbar_40nm.xml. These architectures are now more heavily commented and suitable for work in a grad course (ECE 1756). #### Description I cut the logic block areas...

vaughnbetz

When running parse_vtr_flow it prints out the result to the standard out of the terminal and no file is created. The documentation (https://docs.verilogtorouting.org/en/latest/vtr/parse_vtr_flow/) explicitally says: > The script will produce...

stef9998

Global Nets Routing constraints

7

This branch introduces support for designating any net as global by utilizing a VPR constraints XML file, enabling users to define the routing method for each global net. Here is...

kimiatkh

Support 3D Custom Switch Blocks

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#### Description This pull request support 3d custom switch blocks in the architecture file and automatically add the inter-die edges between tracks in different layer to RR graph. #### Types...

saaramahmoudi

Hi. I am trying to connect a tile pin to other tiles but current direct-connection method only supports chain-style connection. Is there any way to do that?  Thanks.

mustafaarslan0