vtr-verilog-to-routing
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Add the ability to perform detailed routing with different channel widths
Hi, I am a BYU CCL student working with Jeff Goeders and have been working on an improvement to the detailed routing so that we can specify different channel widths and distributions in the x and y direction.
Proposed Behaviour
This change would allow the user to specify a different channel distribution and peak in the x and y directions for detailed routing.
Current Behaviour
Currently detailed routing is only supported on FPGAs with all channels of equal width. If you attempt to use channels of different widths in the x and y direction you receive a fatal error due to the checks in CheckSetup.cpp
Possible Solution
Removing the check in CheckSetup.cpp seems to allow detailed routing to be performed on an architecture with different x and y channel widths. However, this causes the regression test width calculator to incorrectly pick an odd numbered width for a unidirectional graph. This is fixed by adding in a conditional statement that will only allow odd widths for bidirectional graphs and will round odd widths for unidirectional graphs to the nearest even number.
Context
We are trying to create an approximate capture of Xilinx-style FPGA architectures in the VTR architecture description language, and being able to specify channel widths is essential to creating this approximation.