vtr-verilog-to-routing
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Published
20 hours ago •
verilog-to-routing
verilog-to-routing
Fix 3D SIV Delay & Median Move
- Add the scaled delay from the "koios_3d" benchmark into the 3D SIV-like architecture. The inter-die delay is calculated by multiplying the delay of the L4 segment by the ratio of the inter-die delay to the L4 delay of the Koios_3D architecture.
- Fix median/weighted median move to get the median layer of bounding boxes instead of pins (as it is the case for choosing x and y locations)
