Craig Topper

Please retitle this patch and update the description. The only thing in this patch is a new tablegen feature that should be described on its own. The RISC-V use case...

> Sending out one last ping before I land this. I've rebased it and done another look over, it still seems correct to me. > > > > This PR...

> > > Will it be reserved or not for instructions (vghsh and vgmul) , if the vd register group overlaps with the vs2 register group. > > > >...

> > > > > Will it be reserved or not for instructions (vghsh and vgmul) , if the vd register group overlaps with the vs2 register group. > >...

> Zvkgs: Adding .vs variants to vghsh and vghmul > should depend on Zvkgs Is the second line supposed to say Zvkg rather than Zvkgs?

Is there any concern that the name `Zvkgs` is too similar to the existing `Zvksg`? Though this isn't the first time we had such similar names, we have Zbc and...

Is unaligned scalar really supported in hardware on C908, or is it emulated via a trap and the trap handler doesn't know how to emulate vector?

> https://lists.riscv.org/g/sig-vector/topic/questions_about_zicclsm/105531858?p=,,,20,0,0,0::recentpostdate/sticky,,,20,2,0,105531858 Based on the above thread, the description of "misalign" for vector in Zicclsm should be consistent with "8. Vector Memory Alignment Constraints" without making additional requirements for element...

> Beside, the profile does not seem to involve whether the misalignment for vectors is regarding the entire vector register or the elements (which logically is the content of the...

> Zicclsm is not an arch extension in the full sense of the word. It is still called an extension name, but it really is just putting a name to...