Craig Topper comments

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                                            Craig Topper

Effecient way to add an integer and floating point ?

You should also use the x0, x0 form of vsetvli when changing vtype if you're not expecting vl to change.

upper bits for vmv.x.s when SEW>XLEN

Which compiler are you using? clang emulates `vmv_x_s_i64m1_i64` on rv32 with multiple instructions since a single vmv.x.s can only return 32 bits on rv32. https://godbolt.org/z/5zKTbvMba

Behavior of -march=zcf on rv64. Behavior of F+Zce on RV64.

This my LLVM patch. https://reviews.llvm.org/D153742 It includes an error for Zcf on RV64. If Zce is specified with F, it only enables Zcf for RV32. Couple additional questions. Does Zcf...

Behavior of -march=zcf on rv64. Behavior of F+Zce on RV64.

Any progress on getting the spec updated?

[llvm][RISCV] Support RISCV vector tuple for llvm types

This should probably be posted as an RFC on discourse.

[llvm][RISCV] Support RISCV vector tuple for llvm types

> Have you ever tried the target extension type yet? > > * https://reviews.llvm.org/D135202 > * https://discourse.llvm.org/t/rfc-adding-opaque-types-to-llvm-ir/ > * https://reviews.llvm.org/D141899 Is there any SelectionDAG support for target extension types?

Craig Topper

Effecient way to add an integer and floating point ?

upper bits for vmv.x.s when SEW>XLEN

Behavior of -march=zcf on rv64. Behavior of F+Zce on RV64.

Behavior of -march=zcf on rv64. Behavior of F+Zce on RV64.

[llvm][RISCV] Support RISCV vector tuple for llvm types

[llvm][RISCV] Support RISCV vector tuple for llvm types

[llvm][RISCV] Support RISCV vector tuple for llvm types

interrupted by SIGSEGV on riscv64

interrupted by SIGSEGV on riscv64

Possible improvement for SimplifyDemandedBits for Mul