Craig Topper

Question on vl=vtype.vsew/128

1

Multiple instruction definitions use the sentence `In order to properly specify the number of elements, vl needs to be set to vl = vtype.vsew/128`. Isn't vtype.vsew always a value less...

Possible improvement for SimplifyDemandedBits for Mul

5

If the RHS is a constant with X trailing zeros, then the X MSBs of the LHS are not demanded. I don't have any plans to do anything with this...

[Target][RISCV] Add HwMode support to subregister index size/offset.

3

This is needed to provide proper size and offset for the GPRPair subreg indices on RISC-V. The size of a GPR already uses HwMode. Previously we said the subreg indices...

Could shift by 0 on vsll/vsrl/vsra.vi be used to encode shift of 32 instead?

3

Since shifting by 0 is useless, could this encoding be used to increase the shift amount range to include 32? I believe RV128C does something similar with C.SLLI to encode...

Behavior of -march=zcf on rv64. Behavior of F+Zce on RV64.

8

Since Zcf doesn't contain any instructions on RV64. Should toolchains reject it or accept it? The spec says "Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf". Zcf...

Previously we used a lambda. #96174 is proposing to use equal_range for some cases instead of lower_bound. This requires two different comparison functions since KeyType and IndexType are different types....