Craig Topper comments

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                                            Craig Topper

condition statement is not correct in sockaddrToInetAddress

> > This will fix RISC-V to stop trying so hard to use a single branch. Pretty sure I have this removed for our cores in our downstream branch. >...

condition statement is not correct in sockaddrToInetAddress

> aiui the claim is that this code references off the end of a sockaddr_in. which can't happen on Android because bionic will only ever give you a sockaddr_storage, which...

[RISC-V][SiFive] `sifive_vector.h` doesn't work in C++?

cc: @eopXD

[RISCV] Unnecessary move of undefined with subregister liveness enabled

cc: @BeMg

llvm function multi-versioning

Kito filed an issue here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35

Signed averaging addition through vaadd

I think @sun-jacobi wants 0+-1 to give 0, but RDN would give -1. Using RUP with give 0, but would make 0+1 give 1.

example of vmv.v.* is inconsistent with the definition in spec-1.0.pdf?

The assembly parser does not allow `v0.t` as an operand to vmv.v.x. So the code is invalid.

[question] Does V extension implies F and D?

This is documented in "18. Standard Vector Extensions" section of the vector spec. ``` The V extension depends upon the F and D extensions... ```

Effecient way to add an integer and floating point ?

You can put the e32 vsetvli before the vle8. vle8 will load 8-bit elements regardless of sew.