Craig Topper

Is LLVM misidentifying a znver3 as znver4?

Do we need to refine the hwprobe interface to have fast vector misaligned vs fast scalar misaligned?

There is no instruction scheduling for RISC-V vectors. vsetvls that aren't explicitly from vsetvl/vsetvlmax intrinsics are inserted on demand. All instructions are created with extra operands holding their lmul, sew,...

> > There is no instruction scheduling for RISC-V vectors. > > vsetvls that aren't explicitly from vsetvl/vsetvlmax intrinsics are inserted on demand. All instructions are created with extra operands...

> > > > There is no instruction scheduling for RISC-V vectors. > > > > > > vsetvli intrinsics are allowed to CSE as of last week. > >...

> I believe @appujee refers to the 3d task: > > > Eliminate redundant vsetvl instructions. If we are not doing it already, a simple reaching definition analysis should accomplish...

It looks strange to me. What happens if you change the code to ``` if (ss.ss_family == AF_INET6) { const sockaddr_in6& sin6 = reinterpret_cast(ss); if (IN6_IS_ADDR_V4MAPPED(&sin6.sin6_addr)) { // Copy the...

The current code does ``` const sockaddr_in6& sin6 = reinterpret_cast(ss); if (ss.ss_family == AF_INET6 && IN6_IS_ADDR_V4MAPPED(&sin6.sin6_addr)) ``` No fields are accessed until after the `&&` but the cast did occur...

This will fix RISC-V to stop trying so hard to use a single branch. Pretty sure I have this removed for our cores in our downstream branch. ``` diff --git...

> This is a bug in the code and not compiler. the reinterpret_cast is to a **reference** and in C++ references can't be null. Is it a code bug? If...