Verilog topic
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
cpu11
Revengineered ancient PDP-11 CPUs, originals and clones
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
zx-sizif-512
ZX Spectrum CPLD-based clone for rubber case
OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
sv2v
SystemVerilog to Verilog conversion
FPGA-peripherals
:seedling: :snowflake: Collection of open-source peripherals in Verilog
ice40_ultraplus_examples
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
apple-one
An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA