Verilog topic
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
poprc
A Compiler for the Popr Language
sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
hdl_checker
Repurposing existing HDL tools to help writing better code
fomu-workshop
Support files for participating in a Fomu workshop