asic-design topic

VeeR EH1 core

chipsalliance

VeeR EL2 Core

chipsalliance

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

hughperkins

QKeras: a quantization deep learning library for Tensorflow Keras

google

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

stnolting

Standard Cell Library based Memory Compiler using FF/Latch cells

AUCOHL

Open Application-Specific Instruction Set processor tools (OpenASIP)

cpc

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

sdnellen

An AXI4 crossbar implementation in SystemVerilog

dpretet

A place to keep my synthesizable verilog examples.

JeffDeCola