gtkwave topic
vcd
VCD file (Value Change Dump) command line viewer
simavr
simavr is a lean, mean and hackable AVR simulator for linux & OSX
hdl-tools
Facilitates building open source tools for working with hardware description languages (HDLs)
svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
docker
Scripts to build and use docker images including GHDL
my-verilog-examples
A place to keep my synthesizable verilog examples.
vdt-plugin
mirror of https://git.elphel.com/Elphel/vdt-plugin
iverilog-tutorial
Quickstart guide on Icarus Verilog.
rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog