Damien Pretet

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

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An AXI4 crossbar implementation in SystemVerilog

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Repository gathering basic modules for CDC purpose

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SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

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Vim plugin to create Neovim leader key menu

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SystemVerilog Logger

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RISCV CPU implementation in SystemVerilog

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