neorv32 topic
neorv32
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpga_puf
:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
riscv-gcc-prebuilt
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
riscv-debug-dtm
🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
SweetAda
Ada-language framework
neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.